Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples.
Hybrid bonding is one type of bonding procedure for 3DICs, wherein two semiconductor wafers are bonded together using a hybrid bonding technique. Some methods of forming 3DICs are described in patent application: Ser. No. 13/488,745, filed on Jun. 5, 2012, entitled, “Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers,” which application is hereby incorporated herein by reference.
Corresponding numerals and symbols in the different FIGURES generally refer to corresponding parts unless otherwise indicated. The FIGURES are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.